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Electrical Characteristics
Figure 10 provides the AC test load for the DDR bus.
Output
Z 0 = 50 Ω
R L = 50 Ω
V DDDDR /2
Figure 10. DDR AC Test Load
2.6.5
2.6.5.1
Serial RapidIO Timing and SGMII Timing
AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK
Table 24 lists AC signal specifications.
Table 24. SD n _REF_CLK and SD n _REF_CLK AC Signal Specifications
Parameter Description
REFCLK cycle time
Symbol
t REF
Min
—
Typical
10 (8, 6.4)
Max
—
Units
ns
Comments
8 ns applies only to serial RapidIO system
with 125-MHz reference clock. 6.4 ns
applies only to serial RapidIO systems with
a 156.25 MHz reference clock.
Note:
SGMII uses the 8 ns (125 MHz)
value only.
2.6.5.2
Signal Definitions
LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential
signals. Figure 11 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD)
or a receiver input (RD and RD). Each signal swings between voltage levels A and B, where A > B.
A
B
TD or RD
TD or RD
Differential Peak-Peak = 2 × (A – B)
Figure 11. Differential V PP of Transmitter or Receiver
Note:
42
This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/
SRIO_RXD/SRIO_RXD respectively.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
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